1. Field of the Invention
The invention relates to the field of propulsion control system central processing unit (CPU) boards, and more particularly, to bus interface controller design in a CPU board in an Intel 80386 based propulsion control system for use with subway cars or the like.
2. Background Information
A propulsion control system for an advanced design subway car requires high-speed data acquisition, an ability to communicate with a host computer, and an ability to communicate to control slave input/output (I/O) boards for controlling servo systems of the subway car. These varied requirements have caused compromises in communications bus design in the past, and thus limited overall system performance and efficiency.
There are known a variety of buses, bus interfaces, and bus controllers in various microprocessor systems. One known industrial bus standard is the IEEE 796, or Multibus I, and another is the IEEE 1296, or Multibus II. "Multibus" is a trademark of the Intel Corporation for its unified bus architecture, which uses a single integrated bus for data, address and control information. The Intel Multibus is used, for example, for connecting random access memory (RAM), read only memory (ROM) and input/output (I/O) boards in a microprocessor based system. The Multibus carries five types of signals, including data, address, control, multilevel interrupt and timing signals. Modules connected to the bus act as either masters or slaves, masters having the ability to control the bus. Arbitration logic is provided for on the bus to handle requests from multiple bus masters. Data rates on the bus are a factor of the master and slave devices data rates. The Intel bus is configured with two connectors, the primary (P1) and the secondary (P2) connectors. P1 signals include the address, data, control and interrupt signals, as well as the power supply. Most of the signals on the bus operate with negative logic, i.e., they are true when low.
The Multibus I and Multibus II busses are both usable with Intel IAPX 86 CPU based systems, for instance an 80386 CPU based system. Various Multibus I and Multibus II interfaces are known. A device attached to a Multibus I interface has the capability to operate as a bus master and share a bus with other masters that reside on the bus. A device on the Multibus I interface also has the capacity to generate and receive both vectored and nonvectored interrupts as well as read/write references to input/output (I/O) and memory space. Because of the bus protocol used on the Multibus I, and other factors, it is suitable for communication with relatively slow slave I/O boards and the like. The Multibus II, on the other hand, allows interprocessor communications via message passing, and is suitable for high-speed communications.
In typical Multibus I designs, latching of data transceivers is required. Also, the existing devices, for instance the Intel 8288 and 8289 bus controller and arbiter respectively, limit the achievable data throughput of the bus system. Improved performance and a marriage of Multibus I and II capabilities in an integrated system are desirable.
Therefore, a propulsion control CPU board which overcomes the above limitations and provides system design flexibility by having both Multibus I and II interfaces on a single 80386 CPU board is proposed.